1. Field of the Invention
The present invention is generally related to a method of fabricating a board and its structure, and in particular, to a method of fabricating a board having high-density core layer and the structure thereof.
2. The Prior Arts
With the trend of electronic products becoming smaller, thinner, lighter, and shorter and at the same time having more additional functions, the number of I/Os residing on the chips is rapidly increased. The corresponding electronics packaging technology has also been evolving to accommodate the diverse integrated circuits. Nowadays, most high-level products adopt the flip-chip technology; the package density has line width dropped from 90 nm to 65 nm, and even to 45 nm. Meanwhile, the line width on the IC board has become thinner, going from 50 μm to 20 μm (pitch 40 μm), and even to 15 μm (pitch 30 μm).
Apart from the earlier packaging technologies such as dual in line package (DIP), there are many other packaging technologies such as the chip carrier (CC), flip chip (FC), pin grid array (PGA), tape carrier (TC), hermetic package, ball grid array (BGA), quad flat package (QFP), lead on chip (LOC), chip scale package (CSP), bare die, tape carrier package (TCP), etc.
Of all these packaging boards, the line width and the line width/line spacing (L/S) of VOP (via on plated through hole) made by the traditional FC, CSP technologies cannot reach 40 μm or below, which becomes a bottleneck in the reduction of the overall board density.